The present invention relates to a recording and reproducing apparatus for reproducing video data recorded on a recording medium such as a disk or a magnetic tape, a video data decoding apparatus and a video data reproducing apparatus for use with an information transmission system.
A transmission side of an information transmission apparatus or a recording side of a recording and reproducing apparatus using a disk or a magnetic tape as a recording medium has hitherto used a motion encoder shown in FIG. 1, and a reproducing side thereof has hitherto used a motion decoder shown in FIG. 2. The motion encoder shown in FIG. 1 and the motion decoder shown in FIG. 2 shall be in accordance with a storage moving image coding standard standardized based on a standardization work promoted by an MPEG (moving picture image coding experts group) system.
The motion encoder shown in FIG. 1 comprises frame memories (FMs) 201, 202, 203 for sequentially storing therein video data supplied thereto from an input terminal 200, a selector 204 for selectively outputting outputs from these frame memories 201, 202, 203 in response to a control signal supplied thereto from a system controller 226, a motion detection block for obtaining motion vector data by executing a motion detection, a motion-compensation block for executing a motion-compensation based on the motion vector data calculated by the above motion detection block, an adding circuit 207 for calculating a difference between macroblock data of 16 lines.times.16 pixels supplied thereto from the selector 204 and motion-compensated macroblock data of 16 lines.times.16 pixels supplied thereto from the motion-compensation block, an inter/intra judgement circuit 208 for selecting either the macroblock data supplied thereto from the selector 204 or difference data supplied thereto from the adding circuit 207, a switch 209 for selecting either the macroblock data supplied thereto from the selector 204 or the difference data supplied thereto from the adding circuit 207 under control of the inter/intra judgement circuit 208, a compressing and encoding block for compressing and encoding an output from the switch 209, and the system controller 226 for controlling the above-mentioned circuit elements.
When video data are sequentially inputted to the input terminal 200, the inputted video data are sequentially stored in the frame memory 201, video data that has been read out from the frame memory 201 during the next one frame period are sequentially stored in the frame memory 202 and video data that has been read out from the frame memory 202 during the next one frame period are sequentially stored in the frame memory 203, after a time period of 3 frames is elapsed, video data of a first frame is stored in the frame memory 203, and video data of a third frame is stored in the frame memory 201, respectively. Accordingly, if the output of the frame memory 202 is set to video data of present frame, then the output of the frame memory 201 becomes video data of a future frame, and the output of the frame memory 203 becomes video data of a past frame. The output of the macroblock unit from the frame memory 201 will hereinafter be referred to as "macroblock data of future frame", the output of the macroblock unit from the frame memory 202 will hereinafter be referred to as "macroblock data of present frame, and the output of the macroblock unit from the frame memory 203 will hereinafter be referred to as "macroblock data of preceding frame", respectively.
The compressing and encoding block comprises a DCT (discrete cosine transform) circuit 210 for transforming the macroblock data or difference data from the switch 209 at the block unit of 8 lines.times.8 pixels from a DC component to a high-order AC component, a quantizing circuit 211 for quantizing coefficient data supplied thereto from the DCT circuit 210 at a predetermined quantization step size, a VLC (variable length code) encoder 212 for variable-length-coding the coefficient data supplied thereto from the quantizing circuit 211 by a suitable method such as run-length-coding method or Huffman-coding method, and an encoding circuit 213 for encoding the variable-length-coded data supplied thereto from the VLC encoder 212 by adding an inner parity and an outer parity for recording or transmission to provide data in the form of a product code.
The motion detection block comprises a motion detecting circuit 205 for obtaining motion vector data by effecting a motion detection on the macroblock data of the preceding frame supplied thereto from the frame memory 201 and the macroblock data of the present frame supplied thereto from the frame memory 202, and a motion detecting circuit 206 for obtaining motion vector data by effecting the macroblock data of the future frame supplied thereto from the frame memory 203 and the macroblock data of the present frame supplied thereto from the frame memory 202.
The motion-compensating block comprises an inverse-quantizing circuit 215 for obtaining the coefficient data of the DCT circuit 210 by inverse-quantizing the coefficient data supplied thereto from the quantizing circuit 211, an IDCT (inverse discrete cosine transform) circuit 216 for inverse-discrete-cosine-transforming coefficient data supplied thereto from the inverse-quantizing circuit 215 into the original macroblock data or difference data, an adding circuit 217 for adding the output from the IDCT circuit 216 and the motion-compensated macroblock data, a switch 218 for supplying the output of the adding circuit 217 and the output of the IDCT circuit 216 on the basis of a switching control signal supplied thereto from the inter/intra judgement circuit 208, a frame memory 219 for storing the output from the switch 218 in its storage area, a frame memory 221 for sequentially storing the macroblock data read out from the frame memory 219, a motion-compensating circuit 220 for selecting proper macroblock data from frame data stored in the frame memory 219 on the basis of the motion vector data supplied thereto from the motion detecting circuit 205 and outputting macroblock data thus selected as motion-compensated macroblock data, a motion-compensating circuit 222 for selecting proper macroblock data from frame data stored in the frame memory 221 on the basis of the motion vector data supplied thereto from the motion detecting circuit 206 and outputting macroblock data thus selected as motion-compensated macroblock data, a weighting circuit 223 for weighting the motion-compensated macroblock data supplied thereto from the motion-compensating circuits 220, 222 by weighting coefficient data corresponding to a time distance of present frame, a synthesizing circuit 224 for synthesizing two macroblock data weighted by the weighting circuit 223, and a switch 225 for selectively outputting the motion-compensated macroblock data from the motion-compensating circuit 220, the motion-compensated macroblock from the motion-compensating circuit 222 and the synthesized macroblock data supplied thereto from the synthesizing circuit 224 on the basis of a switching control signal supplied thereto from the system controller 226.
The inter/intra judgement circuit 208 compares dispersed values such as the macroblock data from the selector 204 and the difference data from the adding circuit 207, and selects a smaller dispersed value.
The motion-compensating circuit 220 motion-compensates macroblock data of future frame which precedes the macroblock data of frame outputted from the selector 204 from a time standpoint. The motion-compensating circuit 222 motion-compensates the macroblock data of the past frame which follows the macroblock data of frame outputted from the selector 204 from a time standpoint. The weighting circuit 223 and the synthesizing circuit 224 motion-compensate the future and preceding macroblock data, which are behind or ahead of the macroblock data of the frame outputted from the selector 204 by weighting and synthesizing the two motion-compensated macroblock data supplied thereto from the motion-compensating circuits 220, 222, and obtain synthesized macroblock data of the two motion-compensated macroblock data.
The adding circuit 207 encodes the macroblock data of the frame sequentially outputted from the selector 204 by calculating a difference among the above macroblock data and any one of the outputs from the above three systems, i.e., motion-compensated macroblock data. The difference data from the adding circuit 207 is interframe difference data, and the interframe difference data is encoded. Therefore, this processing is referred to as an "interframe-coding (intercoding). Also, the output from the selector 204 is encoded as it is, and hence this processing is referred to as an "intraframe-coding (intra-coding)".
Video data of respective frames outputted from the selector 204 and encoded are generally referred to as "I picture", "B picture", "P picture", in accordance with their encoded forms.
The I picture is encoded video data of one frame composed of intraframe-coded macroblock data of present frame outputted from the selector 204. The encoding in this case is carried out by the DCT circuit 210, the quantizing circuit 211 and the VLC encoder 212. Accordingly, in the case of the I picture, the switches 209, 218 constantly connect movable contacts c to fixed contacts a under control of the inter/intra judgement circuit 208, respectively. In this case, "present frame" represents macroblock data of frame which is outputted from the selector 204 and encoded (intraframe-coded) as it is or which is outputted from the selector 204 and calculated in difference and then encoded (interframe-coded).
The P picture is data which results from encoding (interframe-coding) difference data between motion-compensated macroblock data of I picture or P picture which becomes a preceding frame from a time standpoint relative to the macroblock data of present frame outputted from the selector 204 and the macroblock data of the present frame or intraframe-coded data of the macrobloock data of the present frame. However, when the P picture is generated, motion vector data for motion-compensating video data provided as I picture is determined on the basis of encoded video data serving as P picture and video data preceding this video data as seen from the sequential order in which they are inputted to the motion encoder.
The B picture is data which results from encoding (interframe-coding) difference data among the macroblock data of present frame outputted from the selector 204 and the following macroblock data of six kinds.
The macroblock data of six kinds are macroblock data of present frame outputted from the selector 204, motion-compensated macroblock data of I picture or P picture which becomes a preceding frame relative to the macroblock data of present frame from a time standpoint, motion-compensated macroblock data of I picture or P picture which becomes a preceding frame relative to the macroblock data of present frame from a time standpoint, interpolation macroblock data generated from the I picture which becomes a preceding frame relative to the macroblock data of present frame outputted from the selector 204 and the P picture which becomes a preceding frame relative to the macroblock data of present frame outputted from the selector 204 from a time standpoint, and interpolation macroblock data generated from the P picture which becomes a preceding frame and the P picture which becomes a preceding frame relative to the macroblock data of present frame outputted from the selector 204 from a time standpoint.
As is clear from the above explanation, the P picture includes data encoded by use of video data of frames except the present frame, i.e., interframe-coded data, and the B picture is composed of only interframe-coded data so that the P picture and the B picture cannot be decoded alone. Therefore, as is well known, a plurality of relating pictures are set to one GOP (Group Of Picture), and the P picture and the B picture are processed at the unit of GOP.
In general, the GOP comprises one or a plurality of pictures, and zero or a plurality of non-I pictures. In the following description, one GOP comprises I picture, P picture and two B pictures for the sake of simplicity.
In the following description, let it be assumed that the B picture results from calculating a difference between video data of preceding and succeeding video data of the B picture and that the P picture is obtained from the I picture. In actual practice, upon encoding, of interpolated macroblock data interpolated in the forward direction motion compensation, interpolation motion compensation, and backward direction motion compensation, macroblock data with a highest coding efficiency is selected. Upon decoding, data is compensated at the macroblock unit similarly to the encoding process. Specifically, in difference data provided within one B picture, motion-compensated data motion-compensated by any one of the forward direction motion-compensation, the interpolation motion-compensation and the backward direction motion-compensation becomes data subtracted from the macroblock data to be encoded. In difference data provided within one P picture, motion-compensated macroblock data motion-compensated by any one of the forward direction motion-compensation or the backward direction motion-compensation becomes data subtracted from the macroblock data to be encoded. Accordingly, in the following description, except when video data of every original frame is referred to as "video data", this "video data" shall be understood as "video data of every macroblock".
An operation of the encoder shown in FIG. 1 will be described below.
The video data supplied to the input terminal 200 is sequentially stored in the frame memories 201, 202, 203. The motion detecting circuit 205 carries out a motion detection based on the preceding frame macroblock data supplied thereto from the frame memory 201 and the present frame macroblock data supplied thereto from the frame memory 202, and supplies resultant motion vector data to the motion compensating circuit 220. On the other hand, the motion detecting circuit 206 carries out a motion detection based on the preceding frame macroblock data supplied thereto from the frame memory 203 and the present frame macroblock data supplied thereto from the frame memory 202, and supplies resultant motion vector data to the motion compensating circuit 222. As described above, the motion detecting circuits 205, 206 obtain motion vector data at every macroblock data.
When the encoder shown in FIG. 1 is supplied with motion vector data indicative of motion vectors between all macroblock data of present frame and all macroblock data of future frame and motion vector data indicative of motion vectors between all macroblock data of present frame and all macroblock data of preceding frame, the above encoder starts the encoding processing.
A manner in which macroblock data outputted from the selector 204 are encoded will be described with reference to also FIGS. 3A and 3B.
FIG. 3A shows vide data of every frame supplied to the input terminal 200, and FIG. 3B shows video data of every frame outputted from the selector 204. Of reference numerals shown in blocks serving as frames, reference numerals indicate the orders of inputted frames. Of reference letters, "B" represents data which is encoded as B picture, "I" represents data which is encoded as I picture, and "P" represents data which is encoded as P pictures, respectively.
Video data shown by arrows depict video data to be encoded, and video data from which arrows are started being drawn depict video data used when the video data to be encoded are encoded. Specifically, arrows in FIG. 3A show frames of video data used as predictive video data when video data of respective frames shown by arrows are encoded. Video data of third frame which becomes B picture by encoding is encoded by calculating a difference between one of video data of second frame which becomes I picture by encoding and video data of fourth frame which becomes P picture by encoding or synthesized video data of these two video data. With respect to P pictures, arrows for indicating the frames used as predictive video data are not shown.
Frames within GOP2 of FIGS. 3A, 3B will be described by way of example. In this case, let it be assumed that video data P4 used as predictive video data of video data B5 shown in FIG. 3A is stored in the frame memory 221 shown in FIG. 1. Further, for the sake of simplicity, it is further assumed that predictive video data from the synthesizing circuit 224 is constantly used to obtain B picture by encoding.
As shown in FIG. 3B, video data I6 is sequentially outputted from the selector 204 at every macroblock data. At that time, the movable contacts c of the switches 209, 218 are connected to intra-side fixed contacts b. Accordingly, after the macroblock data of the video data I6 has been passed through the switch 209, such macroblock data of the video data I6 is sequentially processed by the DCT circuit 210, the quantizing circuit 211, the VLC encoder 212 and the encoding circuit 213, and then outputted through an output terminal 214.
On the other hand, coefficient data of the video data I6 quantized by the quantizing circuit 211 is reconverted by the inverse-quantizing circuit 215 and the IDCT circuit 216 to the original macroblock data of 8 lines.times.8 pixels, and supplied through the switch 218 to the frame memory 219, and thereby sequentially stored in the frame memory 219.
After video data P4 has been stored in the frame memory 221 and the video data I6 has been stored in the frame memory 219, predictive video data from the synthesizing circuit 224 is subtracted from video data B5 outputted from the selector 204 by the adding circuit 207, and thereby resultant difference data is encoded. Accordingly, before the video data B5 is outputted from the selector 204, the video data I6 is stored in the frame memory 201, the video data B5 is stored in the frame memory 202, and video data P4 is stored in the frame memory 203.
In this case, the motion detecting circuit 205 generates motion vector data indicative of macroblocks of the video data B5 coincident with somewhere (macroblock data) of the video data I6 by detecting a motion of the macroblocks of the video data B5 stored in the frame memory 202 and the macroblocks of the video data I6. The motion vector data of every macroblock are used by the motion compensating circuit 220 when corresponding macroblock data within the video data I6 stored in the frame memory 219 are sequentially read out, i.e., motion-compensated.
On the other hand, the motion detecting circuit 206 generates macroblocks of the video data B5 coincident with somewhere (macroblock data) of the video data P4 by detecting a motion of the macroblocks of the video data B5 stored in the frame memory 202 and the macroblocks of the video data P4 stored in the frame memory 203. The motion vector data of every macroblock data are used by the motion compensating circuit 222 when corresponding macroblock data provided within the video data P4 stored in the frame memory 221 are sequentially read out, i.e., motion-compensated.
As the macroblock data of the video data B5 are outputted from the selector 204, the synthesizing circuit 224 outputs synthesized macroblock data of the macroblock data of the motion-compensated video data I6 supplied thereto from the motion compensating circuit 220 and the macroblock data of the motion-compensated video data P4 supplied thereto from the motion compensating circuit 222. This synthesized macroblock data is supplied through the switch 255 to the adding circuit 207. Accordingly, the adding circuit 207 subtracts the synthesized macroblock data from the macroblock data of the video data B5. Difference data obtained by this subtraction is encoded by circuits in the succeeding stage. The above-mentioned processing is effected on all macroblock data of the video data B5.
Video data P8 is to be encoded next. Before video data P8 is outputted from the selector 204, the video data P8 is stored in the frame memory 201, video data B7 is stored in the frame memory 202, and the video data I6 is stored in the frame memory 203.
In this case, the motion detecting circuit 205 generates motion vector data indicative of macroblocks of the video data B7 coincident with somewhere (macroblock data) of the video data B8 by detecting a motion of macroblocks of video data B7 stored in the frame memory 202 and macroblocks of the video data P8 stored in the frame memory 201. The motion vector data of every macroblock are used by the motion compensating circuit 220 when corresponding macroblock data provided within the video data I6 stored in the frame memory 221 are sequentially read out, i.e., motion-compensated. It is to be noted that the macroblock data of the video data I6 are compensated based on the motion vector data obtained from the video data P8 and B7.
As the macroblock data of the video data P8 is outputted from the selector 204, the motion compensating circuit 220 supplies the motion-compensated macroblock data of the video data I6 through the switch 225 to the adding circuit 207. Accordingly, the adding circuit 207 subtracts the motion-compensated macroblock data of the video data I6 from the macroblock data of the video data P8. Difference data thus obtained by the above subtraction is encoded by the respective circuits in the succeeding stage, and outputted through the output terminal 214. The above-mentioned processing is effected on all macroblock data of the video data P8. After the video data P8 has been encoded, the video data I6 stored in the frame memory 219 is stored in the frame memory 221.
During the above-mentioned processing, the encoded data from the quantizing circuit 211 is re-transformed by the inverse-quantizing circuit 215 and the IDCT circuit 216, and supplied to the adding circuit 217. The thus re-transformed difference data is added by the adding circuit 217 with motion-compensated macroblock data supplied thereto from the motion compensating circuit 220 through the switch 225, thereby converted into the macroblock data of the video data P8. The macroblock data of the video data P8 is supplied through the switch 218 to the frame memory 219. The above-mentioned processing is continuously carried out until the storage of the video data P8 in the frame memory 219 is finished.
Video data B7 is to be encoded next. Before the video data B7 is outputted from the selector 204, the video data B8 is stored in the frame memory 201, the video data B7 is stored in the frame memory 202, and the video data I6 is stored in the frame memory 203.
Then, the motion detecting circuit 205 generates motion vector data indicative of the macroblocks of the video data B7 coincident with somewhere (macroblock data) of the video data P8 by detecting a motion of macroblocks of the video data B7 stored in the frame memory 202 and the macroblocks of the video data P8 stored in the frame memory 201. The motion vector data of every macroblock are used by the motion compensating circuit 220 when the macroblock data provided within the video data P8 stored in the frame memory 219 are sequentially read out, i.e., motion-compensated.
On the other hand, the motion detecting circuit 206 generates motion vector data indicative of macroblocks of video data B7 coincident with somewhere (macroblock data) of the video data I6 by detecting a motion of macroblocks of the video data B7 stored in the frame memory 202 and macroblocks of the video data I6 stored in the frame memory 203. The motion vector data of every macroblock are used by the motion compensating circuit 220 when the macroblock data provided within the video data I6 stored in the frame memory 221 are sequentially read out, i.e., motion-compensated.
As the macroblock data of the video data B7 is outputted from the selector 204, the synthesizing circuit 224 outputs synthesized macroblock data of the macroblock data of the motion-compensated video data P8 from the motion compensating circuit 220 and the macroblock data of the motion-compensated video data I6 from the motion compensating circuit 222, and the synthesized macroblock data is supplied through the switch 225 to the adding circuit 207. Accordingly, the adding circuit 207 subtracts the synthesized macroblock data from the macroblock data of the video data B7. Difference data obtained by this subtraction is encoded by the respective circuits in the succeeding stage, and outputted through the output terminal 214. The above-mentioned processing is effected on all macroblock data of the video data B7. After the video data B7 has been encoded, the video data P8 stored in the frame memory 219 is stored in the frame memory 221.
As described above, video data of respective frames of GOP2 are encoded, and video data of other GOPs also are encoded similarly. The system controller 226 adds the motion vector data from the motion detecting circuits 220, 222, data indicative of motion-compensation types (or data indicative of subtracted data upon encoding) and picture type data to the compressed difference data supplied to the encoding circuit 213, and further adds data indicative of the starting portion of GOP to every GOP and data indicative of the encoding order to every GOP. The compressed difference data with these data added thereto is converted by the encoding circuit 213 in the form of the product code as described above, and outputted through the output terminal 214 for recording or transmission.
Examples of the motion detecting circuits 205, 206 shown in FIG. 1 will be described with reference to FIG. 4. A detecting circuit shown in FIG. 4 is adapted to execute a motion detection on the basis of a so-called block-matching. The frame memory 202 shown in FIG. 1 corresponds to a present frame memory 321 shown in FIG. 4, and the frame memories 201, 203 shown in FIG. 1 correspond to a reference frame memory 323 shown in FIG. 4.
The motion detecting circuit shown in FIG. 4 comprises the present frame memory 321 for storing therein video data of present frame, a reference frame memory 323 for storing therein video data of future or preceding frame (reference frame), an address shifting circuit 333 for sequentially supplying difference address data to the reference frame memory 323, an adding circuit 324 for subtracting the pixel data of the reference macroblock from the pixel data of a target macroblock of present frame, an absolute value generating circuit 325 for generating difference absolute value data of a subtracted result from the adding circuit 324, a latch circuit 327 for latching the absolute value data supplied thereto from the absolute value generating circuit 325, an adding circuit 326 for obtaining difference absolute value sum data of every reference macroblock by adding the output of the absolute value generating circuit 325 and the latched output of the latch circuit 327, a memory 328 for storing therein difference absolute value sum data supplied thereto from the adding circuit 326, a minimum value detecting circuit 329 for detecting a minimum value from the difference absolute value sum data stored in the memory 328, a motion vector detecting circuit 330 for obtaining one motion vector data corresponding to one target macroblock on the basis of the minimum difference absolute value sum data supplied thereto from the minimum value detecting circuit 329 and supplying the resultant motion vector data to a controller 329 and the system controller 226 shown in FIG. 1, and a controller 332 for controlling the address shifting circuit 333 on the basis of the minimum difference absolute value sum data supplied thereto from the minimum value detecting circuit 329 and the motion vector data supplied thereto from the motion vector detecting circuit 330 and writing of video data in the present frame memory 321 and reading of video data stored in the frame memory 321.
The motion vector detecting circuit 330 converts inputted difference absolute value sum data into motion vector data by reading motion vector data corresponding to inputted difference absolute value sum data, e.g., longitudinal and lateral shift amount data from a ROM (read-only memory) or the like, for example.
Under control of the controller 332, pixel data of macroblock (8.times.8 pixels or 16.times.16 pixels) serving as a target block is sequentially repeatedly read out from the present frame memory 32. On the other hand, under control of the controller 332, the address shifting circuit 333 sets a search area on the memory space of the reference frame memory 323, sets a reference block of the same size as that of the above macroblock within the set search area, and sequentially supplies address data for sequentially reading pixel data from the reference block to the reference frame memory 323. When the reading of pixel data from the set reference block is all ended, the address shifting circuit 333 shifts the position of the reference block within the search area by one pixel by supplying address data to the reference frame memory 323, and reads pixel data from the reference block shifted by one pixel by sequentially supplying address data to the reference frame memory 323.
The adding circuit 324 subtracts pixel data of the reference block read out from the reference frame memory 323 from the pixel data located within the target block read out from the present frame memory 321. A subtracted result from the adding circuit 324 is supplied to the absolute value generating circuit 325, in which it is converted into absolute value data, and supplied through the adding circuit 326 to the latch circuit 327. The latch circuit 327 latches added result from the adding circuit 326, i.e., difference absolute value sum data, whereby difference absolute value sum data between the target block within the present frame memory 321 and one reference block within the reference frame memory 323 are sequentially stored in the memory 328. Then, finally, difference absolute value sum data of the number corresponding to a large number of target blocks set within the search area with a shift of each pixel are stored in the memory 328.
When all calculations of the pixel data of one target macroblock and the pixel data of a plurality of reference macroblocks within one search area are finished, the minimum value detecting circuit 329 selects difference absolute value sum data of minimum value from all difference absolute value sum data located within the memory 328. Then, the minimum value detecting circuit 329 supplies selected difference absolute value sum data to the motion vector detecting circuit 330, and also supplies a control signal to the controller 332 such that the processing of the next target macroblock is started.
The difference absolute value sum data from the minimum value detecting circuit 329 is supplied to the motion vector detecting circuit 330. The motion vector detecting circuit 330 obtains motion vector data corresponding to the difference absolute value sum data from the minimum value detecting circuit 329. The motion vector data obtained in the motion vector detecting circuit 330 is supplied through an output terminal 331 to the motion compensating circuits 220, 222 and the system controller 226 shown in FIG. 1. Having set the search area by a similar procedure, the controller 332 controls the address shifting circuit 333 and the present frame memory 321 in such a manner that pixel data located within the next target macroblock and pixel data within the reference macroblock are calculated one more time.
U.S. Pat. No. 4,897,720 describes the above block-matching technique.
The motion decoder for decoding data series encoded by the motion encoder shown in FIG. 1 will be described with reference to FIG. 2.
The motion decoder shown in FIG. 2 comprises an expanding block for expanding a compressed data series, a motion-compensating block, an adding circuit 413 for adding an output of the expanding block and an output of the motion-compensating block, a switch 405 for selectively supplying the output of the expanding block and the output of the adding circuit 413 to the above motion-compensating block, and a system controller 414 for controlling the expanding block and the motion-compensating block and controlling the switch 405 by supplying a switching control signal to the switch 405.
The expanding block comprises a decoding circuit 401 for error-correcting the compressed data supplied thereto through an input terminal 400 by use of an inner parity and an outer parity, extracting motion vector data added upon encoding, data indicative of motion-compensation type, picture type data, data indicative of a starting portion of GOP, and data indicative of encoding order, and supplying these extracted data to the system controller 414, a VLC decoder for decoding variable-length-coded outputs from the decoding circuit 401 to provide original quantized coefficient data, a re-quantizing circuit 403 for re-quantizing the coefficient data supplied thereto from the VLC decoder 402 to provide the coefficient data processed by DCT, and an IDCT circuit 404 for inverse-discrete-cosine-transforming the coefficient data supplied thereto from the re-quantizing circuit 403 to provide original data.
The motion-compensating block comprises a frame memory 415 for sequentially storing decoded intraframe-coded data supplied thereto from the IDCT circuit 404 through the switch 404 or added output supplied thereto from the adding circuit 413 through the switch 405 in response to a write/read control signal supplied thereto from the system controller 414, a frame memory 408 for sequentially storing data read out from the frame memory 407 in response to a write/read control signal supplied thereto from the system controller 414, a forward direction motion compensating circuit 409 for reading the macroblock data of the frame memory indicated by the motion vector data supplied thereto from the system controller 414 and supplying the thus read out macroblock data to a switching circuit 412 as motion-compensated macroblock data, a bidirectional motion compensating circuit 410 for reading macroblock data of the frame memories 407, 408 indicated by the two motion vector data supplied thereto from the system controller 414, weighting the macroblock data thus read out, obtaining one synthesized macroblock data by synthesizing two weighted macroblock data and supplying the synthesized macroblock data to the switching circuit 412 as motion-compensated macroblock data, a backward direction motion compensating circuit 411 for reading macroblock data of the frame memory 408 shown by the motion vector data supplied thereto from the system controller 414 and supplying the macroblock data thus read out to the switching circuit 412 as motion-compensated macroblock data, and a switch 412 for selectively outputting outputs from the forward direction motion compensating circuit 409, the bidirectional motion compensating circuit 410 and the backward direction motion compensating circuit 411 in response to a switching control signal supplied thereto from the system controller 414.
An operation of the motion decoder shown in FIG. 2 will be described below.
Reproduced or transmitted compressed data is supplied through the input terminal 400 to this motion decoder and thereby sequentially decoded by the decoding circuit 401, the VLC decoder 402, the re-quantizing circuit 403 and the IDCT circuit 404. At that time, the decoding circuit 401 extracts the motion vector data, the data indicative of motion compensation type, the data indicative of picture type, the data indicative of the starting portion of GOP, and the data indicative of encoding order, and supplies these extracted data to the system controller 414.
A manner in which the data expanded by the expanding block is decoded by the motion-compensating block, the adding circuit 413, the switch 405 and the system controller 414 will be described with reference to FIG. 2 and FIGS. 3A to 3C. Meanings of reference symbols and letters in FIGS. 3A through 3C were already described when the operation of the motion encoder has been described so far, and therefore need not be described.
Data are supplied to the input terminal 400 in the sequential order shown in FIG. 3B. Initially, the IDCT circuit 404 outputs the macroblock data of the intraframe-coded video data I6. The system controller 414 supplies the switching control signal to the switch 405 so that the switch 405 connects a movable contact c to an intra-side fixed contact a. Accordingly, the macroblock data of the video data I6 outputted from the IDCT circuit 404 is outputted through the output terminal 406, and supplied to the frame memory 407, in which it is stored in response to the write/read control signal supplied thereto from the system controller 414.
When the macroblock data of the video data I6 is stored in the frame memory 407, difference data of the next video data B5 is outputted from the IDCT circuit 404. The system controller 414 supplies the switching control signal to the switch 405 so that the switch 405 connects the movable contact c to an inter-side fixed contact b. The system controller 414 further supplies the switching control signal to the switch 412 so that the switch 412 connects a movable contact d to a fixed contact b. On the other hand, the bidirectional motion compensating circuit 410 reads macroblock data of corresponding video data I6 from the frame memory 414 and macroblock data of corresponding video data P4 from the frame memory 408 in response to two motion vector data sequentially supplied thereto from the system controller 414, weights and synthesizes the two macroblock data thus read out to thereby obtain one synthesized macroblock data.
Therefore, at the time the difference data of the video data B5 is outputted from the IDCT circuit 404 and supplied to the adding circuit 413, the motion-compensated macroblock data (synthesized macroblock data) from the bidirectional motion compensating circuit 410 is supplied through the switch 412 to the adding circuit 413. Thus, the adding circuit 413 adds the difference data of the video data B5 and the synthesized macroblock data which results from synthesizing the macroblock data of the video data I6 and P4 with the result that the macroblock data of the video data B5 is decoded. Specifically, as shown by an arrow in FIG. 3C, the video data B5 is decoded by the video data P4 and the video data I6.
As already explained in the description of the motion encoder, the macroblock data of the video data B5 is encoded by subtracting the synthesized macroblock data, which results from synthesizing the macroblock data of the video data P4 and the macroblock data of the video data I6, from the macroblock data of the video data B5. Therefore, in order to obtain the macroblock data of the video data B5 by decoding, it is sufficient to add the synthesized macroblock data, which results from synthesizing the macroblock data of the video data P4 and the macroblock data of the video data I6, to the difference data of the expanded video data B5.
When all macroblock data of the video data B5 are decoded, the video data I6 stored in the frame memory 407 is stored in the frame memory 408 in response to the write/read control signal from the system controller 414.
When the macroblock data of the video data I6 is stored in the frame memory 408, the difference data of the video data P8 is outputted from the IDCT circuit 404 next. The system controller 414 supplies the switching control signal to the switch 405 so that the switch 405 connects the movable contact c to the inter-side fixed contact b. Further, the system controller 414 supplies the switching control signal to the switch 412 so that the switch 412 connects the movable contact d to the fixed contact c. On the other hand, the backward direction motion compensating circuit 411 reads out the macroblock data of the corresponding video data I6 from the frame memory 408 in response to the motion vector data sequentially supplied thereto from the system controller 414.
Accordingly, at the time the difference data of the video data P8 is outputted from the IDCT circuit 404 and supplied to the adding circuit 413, the motion-compensated macroblock data from the backward direction motion compensating circuit 411 is supplied through the switch 412 to the adding circuit 413. Thus, the adding circuit 413 adds the difference data of the video data P8 and the motion-compensated macroblock data obtained from the video data I6 so that the macroblock data of the video data P8 is decoded. That is, the video data P8 is decoded by the video data I6. In FIGS. 3A to 3C, arrows indicative of the decoding of the P picture are not shown.
As already described in the description of the operation of the motion encoder, the encoding of the macroblock data of the video data P8 is carried out by subtracting the motion-compensated macroblock data of the video data I6 from the macroblock data of the image data P8. Therefore, in order to obtain the macroblock data of the video data P8 by decoding, it is sufficient to add the motion-compensated macroblock data of the video data I6 to the difference data of the expanded video data P8.
The macroblock data of the decoded video data P8 is outputted through the output terminal 406, and supplied to the frame memory 407. Accordingly, such macroblock data of the decoded video data P8 is stored in the frame memory 407 in response to the write/read control signal from the system controller 414. Therefore, at the time the decoding of the video data P8 is ended, the video data P8 is stored in the frame memory 407, and the video data I6 is stored in the frame memory 408.
Next, the difference data of video data B7 is outputted from the IDCT circuit 404. The system controller 414 supplies the switching control signal to the switch 405 so that the switch 405 connects the movable contact c to the inter-sided fixed contact b. Further, the system controller 414 supplies the switching control signal to the switch 412 so that the switch 412 connects the movable contact d to the fixed contact b. On the other hand, the bidirectional motion compensating circuit 410 reads out the macroblock data of the corresponding video data P8 from the frame memory 407 and the macroblock data of the corresponding video data I6 from the frame memory 408 in response to the two motion vector data sequentially supplied thereto from the system controller 414, and weights and synthesizes the two macroblock data thus read out to thereby obtain one synthesized macroblock data.
Accordingly, at the time the difference data of the video data B7 is outputted from the IDCT circuit 404 and supplied to the adding circuit 413, the motion-compensated macroblock data (synthesized macroblock data) from the bidirectional motion compensating circuit 412 is supplied through the switch 412 to the adding circuit 413. Thus, the adding circuit 413 adds the difference data of the video data B7 and the synthesized macroblock data which results from synthesizing the macroblock data of the video data P8 and the video data I6 with the result that the macroblock data of the video data B7 is decoded. That is, as shown by arrows in FIG. 3C, the video data B7 is decoded by the video data P8 and the video data I6.
As already described in the description of the operation of the motion encoder, the encoding of the macroblock data of the video data B7 is carried out by subtracting the synthesized macroblock data of the macroblock data of the video data P8 and the macroblock data of the video data I6 from the macroblock data of the video data B7. Therefore, in order to obtain the macroblock data of the video data B7 by decoding, it is sufficient to add the synthesized macroblock data of the macroblock data of the video data P8 and the macroblock data of the video data I6 to the difference data of the expanded video data I6.
As described above, video data of frames of GOPs are decoded sequentially. In the example shown in FIGS. 3A to 3C, when decoded video data of frames of GOPs are read out in the sequential order of B1, I2, B3, P4, B5, I6, B7, P8, B9, I10, B11 P12, video data in the GOP are rearranged. It is to be noted that video data within GOPs are rearranged in the order of true frames before being encoded while the order of GOPs is not rearranged.
The motion encoder (see FIG. 1) and the motion decoder (see FIG. 2) are used in a recording and reproducing apparatus such as a VTR or a disk drive, and the information transmitting apparatus such as a communication system. There is then the problem caused when data is reproduced in the reverse direction by the recording and reproducing apparatus or when information transmitted with frames whose orders are reversed in the transmission side is reproduced by the reception side.
A problem caused when data is reproduced in the reverse direction by the recording and reproducing apparatus will be described with reference to FIGS. 5A to 5C.
FIGS. 5A to 5C show a manner in which data encoded by the motion encoder shown in FIG. 1 and recorded on the recording medium by the recording system is reproduced by the reproducing system in the direction opposite to the normal reproducing direction and decoded by the motion decoder shown in FIG. 2 according to the recording and reproducing apparatus. Reference numerals and symbols shown in FIGS. 5A to 5C are similar to those of FIGS. 3A to 3C, and therefore need not be described. FIGS. 5A and 5B are the same as FIGS. 3A and 3B, i.e., show a manner in which data are inputted and encoded. FIGS. 5A and 5B are illustrated in order to supplement the description of FIG. 5C, and therefore need not be described in detail.
If data encoded in the order shown in FIG. 5B and which are recorded on the recording medium in the sequential order of GOP1, GOP2, GOP3 are shifted (or rotated) in the direction opposite to the shifting direction (or rotating direction) of the recording medium upon recording, and reproduced in the opposite direction, then recorded data are reproduced in the sequential order of GOP3, GOP2, GOP1 as shown in FIG. 5C.
Accordingly, when data are decoded by the motion decoder shown in FIG. 2, as shown in FIG. 5C, the video data B9 of GOP3 is decoded by use of video data of P picture of GOP4, not shown, and video data I10 of GOP3, video data B11 of GOP3 is decoded by use of video data I10 of GOP3 and video data P12 of GOP3, video data B5 of GOP2 is decoded by use of video data P12 of GOP3 and video data I6 of GOP2, video data B7 of GOP2 is decoded by use of video data I6 of GOP2 and video data P8 of GOP2, video data B1 of GOP1 is decoded by use of video data P8 of GOP2 and video data I2 of GOP1, and video data B3 of GOP1 is decoded by use of video data I2 of GOP1 and video data P4 of GOP1.
A manner in which video data B1 through B11 are encoded by video data will be described and confirmed one more time with reference to FIG. 5A (as already described with reference to FIG. 3A).
As shown in FIG. 5A, video data B1 of GOP1 is decoded by use of video data of P picture of GOP0, not shown, and video data I2 of GOP1, video data B3 of GOP1 is decoded by use of video data I2 of GOP1 and video data P4 of GOP1, video data B5 of GOP2 is decoded by video data P4 of GOP1 and video data I6 of GOP2, video data B7 of GOP2 is decoded by use of video data I6 of GOP2 and video data P8 of GOP2, video data B9 of GOP3 is decoded by use of video data P8 of GOP2 and video data I10 of GOP3, and video data B11 of GOP3 is decoded by use of video data I10 of GOP3 and video data P12 of GOP3.
As is clear from the above description, of the video data B1 through B11 shown in FIG. 5C, since the video data B9, B5 and B1 are decoded by use of video data different from those used in encoding, a picture quality of reproduced pictures decoded by use of video data which are not deeply related to the video data is quite poor.
As described above, if recorded data are reproduced in the opposite direction when the B picture is encoded by use of P picture of preceding GOP and I picture of present GOP, then video data are decoded by use of video data different from those used in the encoding, resulting in the above problem being caused. However, a manner in which the problem occurs is not limited to the above description. That is, if video data is encoded by use of video data belonging to GOPs which are ahead of or behind, i.e., future or past GOP of GOP to which the corresponding video data belongs, then when video data is reproduced in the opposite direction, inputted video data which are ahead of or behind the GOP to which the corresponding GOP belongs, i.e., video data which belong to future or past GOPs are used. As a consequence, video data different from those used in the encoding are used, resulting in the similar problem being caused.
Troublesome patters will be described below with reference to B picture and P picture belonging to GOP2.
Troublesome pattern in B picture will be described initially.
If B picture belonging to GOP2, for example, is encoded by use of I or P picture belonging to GOP1, then when such B picture is reproduced in the reverse direction, the corresponding B picture is decoded by use of I or P picture belonging to GOP3.
If B picture belonging to GOP2 is encoded by use of I or P picture belonging to GOP3, then when such B picture is reproduced in the reverse direction, the corresponding B picture is decoded by use of I or P picture belonging to GOP1.
If B picture belonging to GOP2 is encoded by use of I or P picture belonging to GOP1 and I or P picture belonging to GOP2, then when such B picture is reproduced in the reverse direction, the corresponding B picture is decoded by use of I or P picture belonging to GOP3 and I or P picture belonging to GOP2.
If B picture belonging to GOP2 is encoded by I or P picture belonging to GOP3 and I or P picture belonging to GOP2, then when such B picture is reproduced in the reverse direction, the corresponding B picture is decoded by use of I or P picture belonging to GOP1 and I or P picture belonging to GOP2.
Troublesome patterns in P picture will be described next.
If P picture belonging to GOP2, for example, is encoded by use of I or P picture belonging to GOP1, then when such P picture is reproduced in the reverse direction, the corresponding P picture is decoded by use of I or P picture belonging to GOP3.
If P picture belonging to GOP2 is encoded by use of I or P picture belonging to GOP1, then when such P picture is reproduced in the reverse direction, the corresponding P picture is decoded by use of I or P picture belonging to GOP3.
This is also true in the case of the information transmitting apparatus. If the information transmission side transmits video data with arrangement of GOP data reversed and such transmitted video data is received at the transmission side, there then arises a similar problem.